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FM3570 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID
Preliminary March 2001
FM3570 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID
General Description
The Fairchild FM3570 replaces the CPU motherboard's configuration switches with an electronic implementation consisting of a 4/5-bit multiplexed, 1-bit latched port, standard 2-wire bus interface, and non-volatile latches. The FM3570 multiplexes the I-port input signals with two internal non-volatile registers that can be loaded through the serial port. The multiplexer is selected via the serial port and defaults to the I-port upon power-up. Pull-up resistors are provided on the input port to accommodate connections to open-drain outputs and to eliminate the need for external resistors. The device has opendrain outputs for easy interface to devices with different VDD levels. The serial port is an IIC compatible slave-only interface and supports both 100kbit and 400kbit modes of operation. The port is used to read the I-Port, write data to the internal non-volatile registers and select whether the I-port or one of the internal nonvolatile registers is output to the Y-port. The FM3570 is fabricated with advanced CMOS technology to achieve high density and low power operation.
Features
I Extended Operating Voltage Range 3.0V-5.5V I IIC Compatible Slave Interface. I ESD performance: Human body model > 2000V I Choice of 2.5V Outputs or Open-Drain Outputs
Block Diagram
Non_Mux_Out
I[4:0]
Y[4:0] Mux1 SOPRA Mux2 SOPRB
MXSB, MXSA
IIC Read Logic
Mux3 Control Logic
MUXSEL OVRD
SDA SCL
IIC Interface
Shift Register
Slave Address Register ASEL Comparator
Start/Stop Logic
(c) 2001 Fairchild Semiconductor Corporation FM3570 Rev. A
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FM3570 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID
Ordering Code FM 3570 XXXX X
Blank X Tube Tape & Reel
M20 MT20
20-Pin SO Package Option 20-Pin TSSOP Package Option
Order Number
FM3570MT20 FM3570MT20X FM3570M20 FM3570M20X
Package Number
MTC20 MTC20 M20B M20B
Package Description
20-Pin TSSOP 20-Pin TSSOP T & R 20 Pin SO 20 Pin SO T & R
For all other combinations, check with Fairchild Marketing/Sales
Pin Connection Diagram
20-Pin Packages FM3570
SCL SDA OVRD I0 I1 I2 I3 I4 Level GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC ASEL WP Non_Mux_Out MUXSEL Y0 Y1 Y2 Y3 Y4
Pin Description
Pin Name
I [0:4] Y [0:4] SCL OVRD WP Non_mux_out MUXSEL EPV ASEL SDA
Description
Data Inputs w/Pullups (10K-40K) Open-Drain Data Outputs Serial Port Clock Input (120K pullup) Override Input. Sets all outputs to 0 Write Protect Input Non-Multiplexed Output Multiplexer Select Input I Port Pull-up Resistor Voltage Address Select Input Serial Port Data I/O (120K pull-up)
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FM3570 Rev. A
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FM3570 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID
Functional Description
The FM3570 block diagram is shown in Figure 1. The device has two primary functional modes of operationi and an additional mode for programming the device.
Serial Output Port Register A(SOPRA) Address: 00H - A read/ write register that contains the new value to be written to output Port-Y and the multiplexer select bit. Serial Output Port Register B(SOPRB) Address: 01H - A read/ write register that contains the new value to be written to output Port-Y and the multiplexer select bit. Parallel Input Port Register (PIPR) Address: 02H - A read-only register that is loaded with the 5-bit value of the I-Port.
Operational Modes
During standard operation, the device will either pass an address to the Y-Port from the I-Port or from an internally programmed value. The I-port values are generated from the motherboard of the system and may be hardwired or driven by another device. Pullup resistors are provided on the device to accommodate this device being driven by open-drain output drivers. The voltage level to which the I-port is pulled up to is determined by the voltage on the EPV pin. The device expects standard CMOS input signals. The the non-multiplexed output is always at CMOS levels. The OVRD (override) input, when set to 0, will cause all the outputs to be set to 0. The WP signal, if set to logic 1, will prevent data from being written to the non-volatile register. The MUXSEL input, when set to logic 0, will select the data from the non-volatile register to drive on the Y0-4 outputs. if set to logic 1, the data from the inputs are selected instead. the non_mux_out latch is transparent when the MUXSEL signal is at logic 0, and will latch when the MUXSEL is in a logic 1 state.
Serial Output Port Register (SOPR)
(Address 000b and 001b) MXSB MXSA 0 b7 0 b6 I5 b5 NMO b4 Data Field I3 b3 I2 b2 I1 b1 I0 b0
b7-b6 - Multiplexer Select Bits (MXSB, MXSA) 00 - Multiplexer passes the SOPR(A). 01 - Multiplexer passer the SOPR(B). 10 - Multiplexer defaults to passing the I-Port Value. b5, b3-b0 - Data Field. New value to be output through the multiplexer. NMO - Non-multiplexed output from internal non-volatile bit.
Output Port: Y0-Y4
The output port is an open-drain output to allow for easy connection to devices running at different voltage levels. The port is always active and either passes the value on the I-Port or the value in the Serial output port (SOPR). Changing the Mux Path is accomplished by writing to b7 of the Serial Input Port Register. SOPR-b7 defaults to a value of zero at power up and the default path is from the I-port though to the output port. The multiplexer only updates when an IIC stop condition is observed.
Parallel Input Port Register (PIPR)
(Address 002b) Address Field 0 b7 0 b6 0 b5 I4 b4 Data Field I3 b3 I2 b2 I1 B1 I0 b0
b7-b5 - Address field. Value is always 000 b4-b0 - Data Field. Value is equal to the value on the I-Port. The external Port Register captures the value on the I-Port. Data is latched into this register on the first clock after a start condition is seen. This insures that a valid value will always be in this register if it is read. This register is a-read only register with respect to the IIC port.
Register Description
The FM3570 has 3 registers in total. These registers are made up of a combination of read-only, write-only and read/write bits. The two registers are listed below.
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FM3570 Rev. A
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FM3570 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID
OVRD 0 0
MUXSEL 0 1
MXSB X X
MXSA X X
Mux_ outputs all 0's Mux_ inputs Mux_ inputs
1
0
1
0
1
0
0
0
1 1
0 0
1 0
1 1
1
1
Note 2
Note 1
From Nonvolatile register (SOPRA) Do not use this c ombination From From No nNonvolatile volatile register register (SOPRB) (SOPRB) Mux_i From No nnputs volatile register (SOPRA or SOPRB)
No n_mux_ ouput all 0's latched NMO (see Note 1) latched NMO (see Note 1) From No nvolatile register (SOPRA)
The IIC protocol uniquely defines START and STOP conditions. A START condition is defined as a HIGH to LOW transition of the SDA signal while SCL is HIGH. A STOP condition is defined as a LOW to HIGH transition of the SDA signal while SCL is HIGH. These are shown in Figure 2.
Device Addressing
The device uses 7-bit IIC addressing.The address has been defined as 1001 110 if the ASEL input is `1' and 0110 111 if the ASEL input is `0'. The address byte is the first byte of data sent after a start condition. This is the only address that this device will respond to. The device will not respond to the general call address 0000 000.
Reading from the Registers
Data can be read from both of the internal registers. All reads are nondestructive and do not change the value in the register or the internal state of the device. When a start condition is received with a read request, both registers can be read out in the following sequence: (1) (2) (3) SOPRA: Serial Output Port Register A SPORB: Serial Output Port Register B PIPR: PORT-I Value
Note 1: Latched NMO state will be the value present on the NMO output at the time of the MUXSEL input transitioning from logic 0 to logic 1 state. Note 2: Output depends on previously selected state of MXSB and MXSA bits written to device.
If so desired, only the SOPRA register can be read. This is accomplished by issuing a stop command after the acknowledge bit for the first byte is read. If no stop is issued, the device will output the registers in the above sequence.
Multiplexer Logic
The output multiplexer logic determines what value is actually output to the Y-port. The value that it output is dependent upon b7-b6 of the SOPRA and SOPRB registers, as well as the external MUXSEL and OVRD inputs. There is only one set of MXS bits in the SOPRA and SOPRB registers. Regardless of whether one writes to SPRA or SOPRB register for setting the MXS bits, the result is the same. These same bits appear in both the registers. If the MUXSEL is logic 0 and OVRD is logic 1, then, if b7, b6 is "10" then the value on the I-port is passed. when b7 is "00" the value of the SOPRA register is passed on the next IIC stop condition, and when b7 is "01" the value of the SOPRB register is passed on the next IIC stop condition. If MUXSEL is logic 1 and OVRD is logic 1, the input lines I0-4 are used to drive the outputs. The above table describes all the combinations.
Writing to the Registers
Data is written to the SOPR registers through the serial port interface. When a write request is received with the Start Address it is assumed that the intent is to write to the SOPR registers. The value placed in the least 6 significant bits of the register contain the new code to be placed in the SOPR A/B registers. The value of the two most significant bits must contain the address of the destination register SOPRA or SOPRB. The internal non-volatile latch takes about 10 ms to update its data. The new data is reflected on the outputs after the internal non-volatile latch is updated, if the corresponding select bits (MXSx, OVRD and MUXSEL) are set to reflect the state of the non-volatile register.
Register Read Sequence
S
S
IIC Interface
The IIC Interface is a standard slave interface. As a slave interface the device will not generate its own clock. Data can be read from and written into the device. Commands for reading and writing the registers are generated by the IIC Master.
Slave Address
1001110
SOPRA R A Register
1
SOPRB A Register
PIPR A Register
AP
A 00bbbbbb A 00bbbbbb A 00bbbbbb A P
Register Write Sequence
S
S
START and STOP Conditions
SDA
Slave SOPRx Address W A Register
1001110 0 A xxbbbbbb
AS
AS
xx = Register Selection bits (MXSB and MXSA) xx = 00 selects SOPRA, 01 selects SOPRB
SCL START Condition STOP Condition
Register Write Sequence using Repeated Start Condition
Slave SOPRA Slave SOPRx S Address R A Register A S Address W A Register A P
S 1001110 1 A 00bbbbbb A S 1001110 0 A xxbbbbbb A P
Figure 2. START & STOP Conditions
Figure 4
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FM3570 Rev. A
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FM3570 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID
Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-stated Outputs Active (Note 2) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or Ground Current per Supply Pin (ICC or Ground) Storage Temperature Range (TSTG) -0.5V to +6.5V -0.5V to +6.5V -0.5V to +6.5V -0.5 to VCC+0.5V -50mA -50mA +50mA 50mA 100mA -65C to +150C
Recommended Operating Conditions
(Note 3)
Power Supply Input Voltage Output Voltage (VO) Output Current IOL Free Air Operating Temperature(TA) Minimum Input Edge Rate (dt/dv) VIN = 0.8V to 2.0V, VCC = 3.0V 3.0V to 5.5V -0.3V to 5.5V 0V to VCC 3mA -0C to +70C 10ns/V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Floating or unused pins (inputs or I/O's) must be held HIGH or LOW.
DC Electrical Characteristics (4.5V < VCC 5.5V unless stated otherwise) Symbol
VIH VIL VOL IIR ICC
Parameter
High Level Input Voltage Low Level Input Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current
Conditions
Min
VCC x 0.7
Max
VCC x 0.3
Units
V V V A A
IOL = 100A IOL = 3mA VI = VIL, VCC = 5.5V VI = VCC or GND VCC (VI, VO) 3.6V -10 300
0.2 0.4 +10 975
DC Electrical Characteristics Extended (3.0V VCC 5.5V unless stated otherwise) Symbol
VIH VIL VOL VOH IIR ICC
Parameter
High Level Input Voltage Low Level Input Voltage Low Level Output Voltage Output High Voltage Input Leakage Current Quiescent Supply Current
Conditions
Min
VCC x 0.7
Max
VCC x 0.3
Units
V V V V A A
IOL = 100A IOL = 3mA 2.3 VI = VIL, VCC = 5.5V VCC (VI, VO) 3.6V -10 300
0.2 0.4 2.5 +10 975
DC Electrical Characteristics I Port Inputs (VCC = 3.3V) Symbol
VIH VIL
Parameter
High Level Input Voltage Low Level Input Voltage
Conditions
EPV = 2.5V EPV = 2.5V
Min
1.2
Max
0.5
Units
V V
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FM3570 Rev. A
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FM3570 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID
AC Characteristics
Symbol Parameter TA = 0C to +70C,CL = 30pF, RL = 500 VCC = 5.0V 0.5V VCC = 3.3V 0.3V Min
tPHL tPLH tPHL tPLH Prop Delay I to Y Prop Delay I to Y Prop Delay to Y (from OVRD or MUXSEL) Prop Delay to Y (from OVRD or MUXSEL)
Units
Max
50 50 50 50
Min
Max
50 50 50 50 ns ns ns ns
IIC AC Characteristics Symbol Parameter TA = 0C to +70C,CL = 30pF, RL = 500 100kHz 400kHz Min
fSCL T1 tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO SCL Clock Frequency Noise Supression Time Constant SCL Low to SDA Data Out Valid Time the Bus must be free before a new Transmission can start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (For a repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time 4.7 0.3 4.7 4.0 4.7 4.0 4.7 0 250 1000 300 0.6
Units
Max
100 100 3.5
Min
Max
400 50 kHz ns s s s s s
0.1 1.3 0.6 0.6 0.6 0.6 0 100
0.9
s ns 300 300 ns ns s
Capacitance (TA = +25C) Symbol
CIN CI/O COUT
Parameter
Input Capacitance (I4-I0) Input/Output Capacitance (SDA) Output Capacitance (Y4-Y0)
Conditions
VI = 0V or VCC, VCC = 3.3 or 5.0 VI = 0V or VCC, VCC = 3.3 or 5.0
TA = +25C Typical
6 7 7
Units
pF pF pF
Non-Volatile Memory Characteristics Parameter
Data Retention Number of writes
Specification
10 years minimum 1,000,000 cycles
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FM3570 Rev. A
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FM3570 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID
Physical Dimensions inches (millimeters) unless otherwise noted
0.496 - 05.12 [12.598 - 13.005] 20 11
0.394 - 0.419 [10.008 - 10.643] 30 TYP Lead No. 1 IDENT 1 10 0.010 MAX [0.254]
0.291-0.299 [7.391- 7.595] 0.010 - 0.029 x45 [0.254 - 0.737] 0.093 - 0.104 [2.362 - 2.642] 0.004-0.012 [0.102-0.305] TYP
8 Max Typ All Leads
0.009-0.013 [0.229-0.330] TYP All Leads
0.004 [0.102] All Leads Tips
Seating Plane 0.016 - 0.050 [0.406 - 1.270] Typ All Leads 0.050 [1.270] TYP 0.014-0.020 TYP [0.356-0.508] 0.008 TYP [0.203]
0.014 [0.356]
Molded Small Outline Package (M) Order Number FM3570M20 Package Number M20B
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FM3570 Rev. A
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FM3570 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID
Physical Dimensions inches (millimeters) unless otherwise noted
Molded Thin Shrink Small Outline Package (MT) Order Number FM3570MT20 Package Number MTC20
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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